1. Field of the Disclosure
The present invention relates to a metal filling device for a through-via-hole formed in a wafer and a filling method using the same, more particularly, to a device of filling in a through-via-hole of a semiconductor wafer metal melted by pressure difference generated between an upper portion and a lower portion on and under a wafer, to be applicable to a micro through-via-hole having 30 μm or less diameter, and a filling method using the same.
2. Discussion of the Related Art
With a recent trend of light, thin, small and short electronic machines, demands for microminiaturizing a semiconductor package used in an electronic machine haven been increasing.
A two-dimensional arrangement of such the semiconductor package reaches the limit in representing a desired size and capacity. Because of that, three-dimensional package technology enabling semiconductor chips multi-layered three-dimensionally gains attention.
The 3D package technology has to represent various functions, with a light and small size, to enable a high-technology semiconductor such as a memory requiring a high capacity and low electricity or SOC (System On Chip) with high performance. This may be solved by multi-layering thin semiconductor chips and these chips are electrically connected through via-holes, instead of wire-bonding conventionally used in the prior art, to be multi-layered. Advantages of such the 3D package may be a size and weight reduction, improvement of electrical performance, improvement of device performance per unit area and reduction of production cost.
Based on these advantages, a new 3D package technology has been under development and both of the size of the via-hole and the thickness of the wafer have been getting smaller to enable new and various functions. According to ITRS 2007 report, it is predicted that the thickness of the wafer will be 80 μm or less and that a diameter of the via-hole will be 5 μm or less.
However, open Korean Patent number 10-2008-0068334 of which application number is 10-2007-005948 discloses a method of filling in a via-hole Tin or solder melted after electroplating Tin or solder on an inner wall of a via-hole. This is for filling metal in the via-hole having a closed bottom, not a through-via-hole, and it uses an electroplating method and reflow method. Here, the electroplating method may have a big different result according to composition of electroplating solution, the kind of additive, current density, a current mode. Because of that, it is difficult to acquire an optimum work condition. Moreover, that application uses a pressure applying method, a solder ball melting method and a screen printing method. According to the pressure applying method, pressure is applied to molten material after a semiconductor chip having a via-hole formed therein is charged in Tin or molten Tin and a melted Tin or solder is filled in the via-hole. According to the solder ball melting method, a tin or solder ball or like placed on a top of a via-hole is dissolved to be filled in the via-hole. According to the screen printing method, Tin or solder paste is filled in a via-hole in screen-printing only to be melted. However, these methods would generate disadvantages of failing to fill Tin or solder in edge portions of the via-hole.